1. Field of the Invention
The present invention relates to a signal processing circuit, an image processing apparatus, and a signal processing method.
2. Description of the Related Art
With the recent development of digitization of information, image processing apparatuses, such as printers and facsimiles used for outputting digitalized information and scanners used for digitalizing documents have become indispensable. Such image processing apparatuses are often designed as a multifunction peripheral (MFP) capable of being used as a printer, a facsimile, a scanner, and a copier by including an image capturing function, an image forming function, and a communication function, for example.
In such image processing apparatuses, an image processing application specific integrated circuit (ASIC) that performs processing of read data received from a scanner and processing of image data to be input to a plotter for forming and outputting an image operates based on a clock supplied from a clock generating device, thereby performing the processing described above.
In regard to such clock control, Japanese Patent Application Laid-open No. 2009-071720, for example, discloses a method for enabling use of different clocks for each of various functions mounted on an ASIC. Furthermore, Japanese Patent Application Laid-open No. 2001-014451, for example, discloses a method for specifying the buffer capacity required at the least for a cooperative section to achieve cooperation between a clock synchronous section, such as a circuit that performs image processing, and an asynchronous section processed by an arithmetic device, such as a central processing unit (CPU).
As disclosed in Japanese Patent Application Laid-open No. 2009-071720 and Japanese Patent Application Laid-open No. 2001-014451, while image processing apparatuses are designed as various models, such as a high-spec model, a cheaper model, and a model specializing in a specific function, these models are different from one another in the clock frequency and the clock supply pattern (hereinafter, referred to as a clock pattern). Examples of the difference include whether a spread spectrum clock (SSC) is provided, whether a phase locked loop (PLL) is mounted on the ASIC, whether a spread spectrum clock generator (SSCG) for the SSC is mounted, and whether a clock needs to be supplied from the ASIC to an external device, such as a scanner and a plotter.
Therefore, the ASIC mounted on each product model needs to be designed in accordance with the clock frequency and the clock supply pattern in each model, resulting in a burden in designing and an increase in cost of the apparatus. However, such problems do not necessarily occur in the image processing ASIC described above. Any signal processing circuit that transfers a signal between an externally connected device and an internal circuit may possibly have the same problems.
Therefore, there is a need for a signal processing circuit that is compatible with various clock patterns.